FIG. 1 is a simplified block diagram showing a conventional digital processor 100 including a core section 110, a data and address arbitration circuit 120, and on-board memory components including a RAM 130 and a ROM 135. Core section 110 includes various pipeline stages and associated registers including, a fetch stage 112, decode stage 114, an execute stage 116, and a write back stage 118. As would be understood by those skilled in the art, instructions to be executed on the processor are fetched or retrieved by means of hardware included in the fetch stage 112. The instructions are then decoded in the decode stage 114 and executed in an appropriate sequence in the execute stage 116. Instructions and data are transmitted to and from core 110 using an instruction address bus 121, an instruction value bus 123, a data address bus 125, and a data value bus 127. Data and address bus arbitration circuit 120 coordinates the transmission of data and instruction values from core 110 to on-board memory components (e.g., a RAM 130 and a ROM 135), which are coupled to buses 121, 123, 125, and 127 through the arbitration circuit 120.
FIG. 2 is a simplified diagram showing a Breakpoint/Watchpoint (BWP) trigger circuit 140, which is typically included in many digital processors, such as processor 100, to monitor instruction addresses or data addresses/values being fetched by the processor core during program execution, and to serve as part of a debugging tool used by programmers and software engineers (developers) during the development of complex programs.
BWP trigger circuit 140 typically includes one or more instruction address registers 147 and data address/value registers 149 that store user-defined addresses/values, and asserts one or more BWP trigger signals (BWP TRIGGER 0 through BWP TRIGGER 3) when an associated “BWP trigger event” occurs (i.e., an address/value stored in registers 147 and 149 matches an address/value transmitted on buses 121, 125, or 127). BWP trigger events generally fall into two categories: instruction BWP trigger events, and data BWP trigger events. Instruction BWP trigger events occur when an instruction is executed whose address (as transmitted on bus 121) matches the address stored in programmable register 147. Instruction BWP trigger events can either be Break Before Make (BBM) events, or Break After Make (BAM) events. BBM events occur when all instructions preceding the instruction associated with the pre-loaded address are retired (executed) by the processor (e.g., in decoder stage 114 of processor core 110). BAM events occur when any architectural state is changed by executing the instruction associated with the pre-loaded address (e.g., in write back stage 118). Data BWP trigger events occur when a data address transmitted on bus 125 and/or a data value transmitted on bus 127 matches the address/value stored in programmable register 149.
The addresses/values stored in programmable registers 147 and 149 are typically set by a program developer as part of an interactive debugging operation used to scrutinize a program's execution. When the address of the code being fetched (or address/value of data being read/written) matches with the address/value stored in programmable registers 147 or 149, then one or more associated BWP triggers are transmitted to either the core 110 (referred to herein as “breakpoint triggers”) or to an external system (“watchpoint triggers”). Thus, BWP trigger circuit 140 facilitates the software development process by allowing the developer to control core 110 (e.g., by executing a halt or trap) when a user-defined breakpoint trigger event occurs (e.g., at a specific processor state), or to generate an external signal indicating a specific processor state when a user-defined watchpoint trigger event occurs.
While conventional BWP trigger circuit 140 provides developers with a useful debugging tool, it is not flexible enough to generate BWP triggers in response to a complex sequence of trigger events. As discussed above, BWP trigger circuit 140 asserts associated BWP triggers when an instruction address or data address/value transmitted on an associated bus matches the values stored in registers 147 and 149. However, as software programs become more complex, developers may wish to generate BWP triggers when a complex sequence of trigger events occurs (e.g., when a specific sequence of instructions are called/executed), something that is not possible with conventional BWP trigger circuit 140.
What is needed is a BWP trigger circuit that provides a developer the option of generating BWP triggers in response to complex combinations of trigger events.